1. Field of the Invention
This invention relates to an integration process in a SOI substrate of a semiconductor device comprising at least a dielectrically insulated well.
The invention relates, particularly but not exclusively, to a process for integrating a BiCMOS technology device in a SOI (Silicon-On-Insulator) substrate.
2. Description of the Related Art
As it is well known, full electrical insulation for one or more devices may be obtained, for example, by integrating a dielectric trench insulating structure so as to create one or more isolation wells wherein such devices can be formed.
Particularly with devices made in SOI substrates, which devices are characterized by a BOX (Buried OXide) layer providing vertical insulation, a dielectric trench side insulating structure is specifically provided for lateral insulation only.
Thus, continuity from the buried oxide layer to the dielectric trench side insulating structure ensures dielectric insulation of devices integrated in the SOI substrates and formed in suitable wells, known as isolation wells, which are surrounded by the BOX layer and the dielectric trench side insulating structure.
Shown schematically in FIG. 1 is a portion 1 of a semiconductor device that includes essentially a dielectrically insulated well 2 according to the prior art.
In particular, the semiconductor device portion 1 includes a substrate region 3, also known as the handle-wafer, which usually provides mechanical support. Where complex devices are integrated, it also serves as an active silicon layer.
Formed onto the substrate region 3 is a buried oxide (BOX) layer 4 which is used for vertical insulation of the well 2, side insulation thereof being provided by means of a side oxidized region that is covered by a nitride layer 6 and is provided at the edges of the well 2 in dielectric contact with the buried oxide layer 4.
In particular, the combination of two side oxidized regions 5 with their nitride layers 6, and the underlying portion of the buried oxide layer 4, forms a so-called dielectric trench insulating structure 7 which is usually filled with a filling material 8, usually polysilicon.
The dielectric trench insulating structure 7 defines, inside the well 2, an integration region 9 (device-wafer) for a variety of components that are thus isolated from the remainder of the semiconductor device.
The surface of the semiconductor device portion 1 should be sufficiently planar to allow the other layers required for integrating components of interest in the well 2 to be grown or deposited. The involved layers may be photoresist, nitride, vapox, oxide, metallization or other layers, for example.
It should be noted here that processes of etching and depositing mutually selective layers are necessary to produce the side insulation, as well as for the planarizing step.
For example, silicon etching to form the dielectric trench insulating structure 7 is to be carried out selectively with respect to the surface layers (such as oxide and/or nitride layers). In particular the presence of the buried oxide layer 4, typical of SOI substrates, makes a complicated process sequence necessary to avoid etching away or damaging the layer 4 during any of the processing steps required to form the electrically isolated well 2.
From U.S. Pat. No. 5,811,315 to W. Yindeepol et al., a method of forming dielectric trench insulating structures in SOI substrates is known, which comprises, in particular, a process sequence for integrating and planarizing deep trenches, and is directed to leave the thickness of a field oxide, preliminarily grown over the silicon wafer surface, unaffected.
Reference will be made now to FIGS. 2A to 2O for a description of this known process sequence.
Starting with a SOI substrate 13 formed onto a conventional substrate 11, and a buried oxide layer 12 (as shown schematically in FIG. 2A), the following layers are formed in this order: a thick oxide layer 14 (also known as field oxide), being grown preliminarily over the silicon surface of the substrate 13; a silicon nitride layer 15, being deposited onto said field oxide 14; and a (VAPOX or TEOS) deposited oxide layer 16, acting as a hardmask, which is deposited onto the previously formed layer 15 of silicon nitride.
The silicon nitride layer 15 is used, in particular, to avoid etching the field oxide 14 away during the step of removing the hardmask layer 16, as later provided after a dielectric insulating trench 17 is formed.
The hardmask layer 16 is purposely coated with a resist layer 18 (as shown schematically in FIG. 2B), and appropriate openings are formed to the same width as the dielectric trenches 17 to be formed, using photolithographic processes well known to the skilled persons in the art. A step is then carried out of dry etching the layers 16, 15 and 14, the etchant chemistry for these layers being selective with respect to the substrate 13.
Thereafter, the resist layer 18 is removed, and the substrate 13 is dry etched down to the buried oxide layer 12 to form the dielectric trench 17 (as shown schematically in FIG. 2C).
To remove crystal damages caused during this etching step along the walls of the dielectric trench 17, a thin oxide layer 19, known as sacrificial oxide, is grown and subsequently removed (as shown schematically in FIGS. 2D and 2E). The thin sacrificial oxide layer 19 is etched using a HF solution. This etching should not be applied for too long, overetching of the buried oxide layer 12 and the field oxide 14 being thus avoided.
A sidewall oxidation process to grow an oxide layer 20 along the sidewalls of the dielectric trench 17 (as shown schematically in FIG. 2F), and a depositing step of a nitride layer 21 all over the surface of the semiconductor device (as shown schematically in FIG. 2G), are then carried out.
The nitride layer 21 is next etched away, anisotropically and selectively with respect to the buried oxide layer 12, but allowed to stay on the sidewall surfaces of the dielectric layer 17 in order to form so-called spacers in contact with the silicon nitride layer 15 (as shown schematically in FIG. 2H). The nitride layer 21 is instead removed from over the hardmask layer 16 and from the bottom of the dielectric trench 17.
It should be noted that the deposition of the nitride layer 21 is also directed to prevent etching through the field oxide 14 as the hardmask layer 16 is removed. For the purpose, the thickness of the hardmask layer 16 is originally selected to ensure that a vertical-wall portion of it will survive the various etching steps and provide good covering of the spacer formed by nitride layer 21, which will serve to keep the side regions of the field oxide 14 intact (as shown schematically in FIG. 2I).
This means that, during the process operations between the two nitride depositions, HF etchings will be applied to remove any residual oxynitride 22 from the interface of the two nitride layers (15 and 21), as shown schematically in FIG. 2J.
Following a step of anisotropically removing the nitride layer 21, the resulting trench 23 is filled with a filling material 24, specifically a polysilicon filling material (as shown schematically in FIG. 2K).
Thereafter, the polysilicon filling material 24 is removed from the surface, which is an endpoint with respect to the hardmask layer 16 (etching back step), thereby to leave some polysilicon 24 inside the trench 23 (as shown schematically in FIG. 2L). At this stage, the polysilicon filling material 24 is overetched slightly so that the following cap oxidizing step can be planar with respect to the field oxide 14.
After this etching back step of the polysilicon filling material 24, the hardmask layer 16 leftover is removed. It is therefore important to have a robust interface provided between the nitride regions 15 and 21 that is capable of withstanding the protracted exposure to the etchant involved in the removal of the hardmask layer 16.
It should be noted that the hardmask layer 16 is not to be removed before the polysilicon filling material 24 is deposited into the trench 23. Otherwise, the buried oxide layer 12 would be removed with it, since, at this stage, the bottom of the trench 23 is not protected by any nitride layer, and the required vertical dielectric insulation of the trench 23, and hence of the well 2, is missing.
Furthermore, even with the polysilicon filling material 24 in the trench 23, a nitride layer 21 would still be necessary to provide side spacers and prevent an etching of the hardmask layer 16 from intruding also into the field oxide 14 (as shown schematically in FIG. 2M).
After removal of the hardmask layer 16, the whole surface of the semiconductor device, excepting the polysilicon filling material 24, will be covered with silicon nitride (layers 15 and 21). An oxidizing step is then carried out to oxidize and plug up dielectrically the polysilicon filling material 24 in the trench 23, thus forming the so-called cap oxide 25 (as shown schematically in FIG. 2N).
At this point, the silicon nitride of the layers 15 and 21 is removed, to leave the well 2 sides insulated dielectrically by the trench 23 thus obtained (as shown schematically in FIG. 2O). The combination of the trench 23 and the buried oxide layer 12 in mutual contact form the dielectric insulation of the well 2.
It thus becomes possible to go through further processing steps and integrate a number of devices in such a well 2, now dielectrically insulated.
Although achieving its object of providing a dielectrically insulated well in a SOI substrate, the above known solution involves a long and complicated procedure, and has technological limitations which demand compromise processing. Particularly overetching, when removing the silicon nitride layer 15, may cause structural problems in the trench 23, as shown schematically in FIGS. 3A and 3B as noted by the pair of arrows.
These problems can be obviated by dry etching, rather than wet etching, the silicon nitride layer 15. In practice, this choice may result in a thin layer 26 of so-called pad oxide becoming damaged which would be present in the active regions of the semiconductor device where no thick field oxide 14 is provided (as shown schematically in FIG. 3C). Before this dry etching can be applied to the silicon nitride layer 15, the pad oxide 26 must be removed and a better quality oxide grown instead, which further lengthens the process sequence.
Also, the thickness of the hardmask layer 16 would exit the etching step for forming the trench 23 with uneven spots.
Finally, the trench 23 must be filled before the hardmask layer 16 is removed, to avoid etching away the buried oxide layer 12. This process limitation introduces some problems to the step of etching back the polysilicon filling material 24. Controlling the planarity of the semiconductor device surface near the trench 23 after said step of etching back the polysilicon filling material 24, is made difficult (as shown schematically in FIGS. 4A and 4B) because the depth to which the polysilicon filling material 24 is etched inside the trench 23 is proportional to the thickness of the hardmask layer 16, and the thickness of the hardmask layer 16 shows unevenness after the etching of the trench 23.
Also described in the aforementioned US patent is an alternative process for removing the hardmask layer 16 before the step of filling the trench 23 with the polysilicon filling material 24, without etching away the buried oxide layer 12.
After completing the process steps just described up to the depositing step of the nitride layer 21, a dry etching step is carried out with different pressure and power parameters with respect to the previous embodiment, so as to retain a residual amount 21* of nitride on the bottom of the trench insulating structure (as shown schematically in FIGS. 5A and 5A-1).
Presently, the hardmask layer 16 is removed, and the steps of depositing, etching back and oxidizing the polysilicon filling material 24 are carried out similarly as in the above-described process sequence (as shown schematically in FIGS. 5B to 5E), the nitride layer 15 is removed, and a trench 23 is thus completed with residual nitride 21* left on the trench bottom (as shown schematically in FIG. 5F).
A first embodiment of the trench 23, shown schematically in FIGS. 6A to 6E, is also described wherein the nitride layer 15 is removed initially to also take away corner edges 27. Thereafter, another nitride layer 28 is grown which conforms with the underlying structure, and the structure is completed by the previously described process steps.
A second embodiment of the known trench 23xe2x80x2, shown schematically in FIGS. 7A to 7E, can be obtained by removing the nitride layer 15 and depositing the polysilicon filling material 24 directly, the structure being completed by the previously described process steps.
The alternative embodiments shown in FIGS. 5A to 5F, and 6A to 6E, provide trench insulating structures which have no nitride layers inside the trenches, thus eliminating the risk of this internal layer of nitride causing stresses and flaws to appear in the SOI substrate next to the trench walls.
In these alternative embodiments, however, the selectivity of some processing steps with respect to others is critical, and calls for a complicated and variously compromised process sequence.
In particular, and as indicated in the aforementioned patent, the buried oxide layer 12 typical of SOI substrates must be protected during the etching steps to form the trench 23.
In addition, the trench 23 is formed after the field oxide 14 is grown, that is after defining the active areas of the components. This requires that the thickness of the field oxide 14 be preserved during the etching steps necessary to form the trench 23.
The above limitations to the process call for depositions of at least two nitride layers, and create problems of selectivity in connection with the required etchings to integrate the trench 23 as well as protect the field oxide 14.
Forming a trench of insulating structure 23 as taught in the aforementioned patent, in accordance with the main process flow and its alternative embodiments, involves long and complicated processing steps, and places constraints on the fabrication of the semiconductor device as a whole.
Integrating dielectrically insulated structures in SOI substrates has a further problem in the quality of the side insulation provided for the well by the trench insulating structure.
For example, the development of flaws from mechanical stress in the silicon regions which surround the trench insulating structure, or the silicon regions near the corners of the well defined by such a structure, where the trench is contacting the buried oxide layer, may lead to leakage, early breakdown, or breakdown instability, especially at high operating voltages of the well.
To remove this critical factor, it has been known to bias the polysilicon trench filling material 24 so as to maintain a stable electrical isolation of the components integrated in the various isolation wells of the wafer. This bias method involves, however, changes to the structure and the process previously described.
Methods of biasing the polysilicon filling material of a dielectric trench consistent with SOI substrate technologies are described in U.S. Pat. No. 5,914,523 to R. Bashir et al., and U.S. Pat. No. 6,071,803 to M. J. Rutten et al., for example.
In particular, the above-mentioned first patent describes a process for obtaining a metallization trench that is partly insulated dielectrically and allows top-bottom contact of the silicon regions located in the handle-wafer and in the device-wafer, in order to overcome problems of integration of ESD structures in dielectrically insulated technologies.
The resulting structure is in contact with the trench filling material, thereby overcoming the problems of unstable insulation mentioned above.
The above-mentioned second patent describes a process for obtaining a trench insulating structure in a SOI substrate. In particular, the process sets out from a trench 23 (FIG. 2N) obtained in accordance with the first patent, and comprises an oxidizing step of the polysilicon filling material 24 of the trench (as shown schematically in FIG. 8A), which results in a nitride layer 29 being formed.
The nitride layer 29 and a portion of the nitride layer 21 are then etched away to leave a side portion 30 of polysilicon exposed (as shown schematically in FIG. 8B).
The exposed polysilicon side portion 30 is 0.5 micron at the deepest.
A further layer 31 of polysilicon is then deposited onto the entire surface of the semiconductor device to cover the formed trench (as shown schematically in FIG. 8C).
It should be noted that the polysilicon layer 31 will be contacting the polysilicon filling material 24 through the exposed polysilicon side portion 30, the depositing step being self-aligned and requiring no additional masking.
Briefly, the bias contact to the trench polysilicon filling material 24 is established by a second polysilicon layer 31, the latter being optionally useful to contact active regions of the components as well.
All of the conventional trench insulating structures in a SOI substrate described hereinabove involve long and complicated sequences of fabrication steps, and place heavy constraints on the construction of the whole semiconductor device, especially the trench, while also creating problems of criticality of the etching steps and selectivity of the materials to be used, which all restrict their applicability.
The underlying technical problem of this invention is to provide a process for integrating a semiconductor device having an insulating structure in a SOI substrate, which process has structural and functional features appropriate to make the process sequence simple and overcome the drawbacks with which conventional processes are still beset.
The disclosed embodiments of the invention include using the nitride layer from the initial step of fabricating the semiconductor device as a hardmask, and forming the dielectric trenches for insulating the well of the semiconductor device before the active areas of the components to be integrated in the well are defined, thereby reducing the number of steps and making the integration process steps simpler and more flexible to carry out.
Based on this principle, the technical problem is solved by an integration process as previously indicated, and more specifically, to an integration process in a SOI substrate of a semiconductor device comprising at least a dielectrically insulated well, which process includes: an oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto said oxide layer; and a masking step, carried out onto said nitride layer using a resist layer and directed to define suitable photolithographic openings for forming at least one dielectric trench providing side insulation for the well.
In accordance with another embodiment of the invention, an integration process in an SOI substrate of a semiconductor device including at least a dielectrically insulated well is provided. The process includes and oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto the oxide layer; a masking step carried out on the nitride layer using a resist layer and defining a photolithographic opening for forming at least one dielectric trench effective to provide side insulation for the well; an etching step of the nitride layer and the oxide layer using the resist layer and the nitride layer as a hardmask; forming at least one dielectric trench and comprising at least one etching step of the substrate, an oxidizing step of at least sidewalls of the at least one dielectric trench, and a filling step of the at least one trench with a filling material; and a step of defining active areas of components to be integrated in the well, carried out after the step of forming the at least one dielectric trench.